A DDR SDRAM having a high-speed data transfer function called a double data rate (DDR) mode is a kind of semiconductor memories, used for a main memory of a computer.
The SDRAM is a DRAM made up such that its interface with an external bus is operated in sync with a clock signal at a fixed cycle. Since the DRAM is made up so as to enable electrical charge to be stored by means of capacitors and transistors, read/write can be freely executed, however, as the electrical charge for storing information will discharge with time, rewriting (refresh) for holding memory content is executed at intervals of a fixed time length. When the computer is turned off, the memory content is erased.
In the DDR mode, a transfer rate of the SDRAM is increased twice as fast as a normal rate. More specifically, synchronous timing is reinforced so as to enable read/write of data to be executed at both the rising edge of, and the falling edge of the clock signal for providing synchronization between a CPU and memories within the computer.
With the DDR SDRAM, there has since been adopted a technique whereby presence of data is notified to the opposite party on the premise that a differential data strobe (DQS) is effective, the technique has hardly had effectively functioned until DDR2. The reason for this is because a clock has been relative low in speed, and testing on data and DQS has been easily conducted on the basis of the clock.
In contrast, in the case of an interface of an SDRAM handling high-speed data, such as a DDR3, DDR-DRAM of the next generation, frequency of a clock fed from a tester is multiplied within a semiconductor memory, serving as a test target or device under test (hereinafter referred to as DUT), by use of, for example, a PLL (Phase Locked Loop) to thereby generate a high speed clock (or example, a reference clock at 133 MHz is multiplied by a factor of 24 within a device to thereby obtain one at 3200 MHz), the interior of the DUT is driven with the use of the clock at a higher speed, and further, in order to provide operation timing inside the DUT, clock matching is executed by use of a DLL (Delay Locked Loop), and so forth.
In JP 2002-230999 A described hereunder, there has been described the structure of a DDR SDRAM, and a test thereon.
With a common tester for conducting a test on those conventional DDR SDRAMs, a time for an input signal from the DUT is set on the basis of a reference timing inside the tester, and by sampling the input signal, and carrying out logical comparison of values thereof, determination on pass/fail is made. This is based on the premise that the DUT is operated in complete sync with basic timing (a clock) fed from the tester.
FIG. 8 is an example of a timing chart of the DDR SDRAM described. In the figure, symbol (a) indicates a system clock generated in the DUT, based on a reference clock inputted from the tester. Symbol (b) indicates a differential data strobe (DQS) outputted from the DUT. Symbol (c) indicates a multi-strobe consisting of a plurality of strobes (in the case of the example, in FIG. 8, 16 strobes), which is a strobe for probing whereabouts of a transition point of DQS. Symbol (d) indicates a histogram, which is found by sampling DQS with the multi-strobe. The transition point of DQS is identified as “somewhere hereabout” on the basis of a peak position in the histogram. Symbol (e) indicates data DQ outputted from the DUT. Symbol (f) indicates strobes for use in sampling DQ, executing operation for adding offset-time Tos required by the device to the peak position in the histogram.
FIG. 9 is an example of a timing chart of DDR2-400. In the figure, parts corresponding to those in FIG. 8 are denoted by like reference numerals. In the figure, symbol (a) indicates a system clock generated in the DUT, (b) indicates the differential data strobe (DQS) outputted from the DUT, (c) indicates the multi-strobe, and (d) indicates data DQ outputted from the DUT. A region within ±500 ps centering around the transition point of the system clock is defined as a significant region of the differential data strobe (DQS), 350 ps from a crossover point of the differential data strobes DQSs is defined as a strobe position of the data DQ, and a region within ±600 ps centering around rising of the system clock is defined as a significant region of the data DQ.
FIG. 10 is an example of a timing chart of DDR3-800. In the figure, parts corresponding to those in FIG. 9 are denoted by like reference numerals. In FIG. 10, 200 ps from a crossover point of the differential data strobes DQSs is defined as a strobe position of the data DQ, and a region within ±150 ps centering around rising of the system clock is defined as a significant region of the data DQ.
FIG. 11 is an example of a timing chart of DDR3-1600. In the figure, parts corresponding to those in FIGS. 9, and 10, respectively, are denoted by like reference numerals. In FIG. 11, 100 ps from a crossover point of the differential data strobes DQSs is defined as a strobe position of the data DQ, and a region within ±150 ps centering around rising of the system clock is defined as a significant region of the data DQ.
However, it is difficult to accurately maintain a positional relationship of an internally generated high-speed clock with the clock inputted from the tester at all times, and in some cases, a positional relationship between the differential data strobe DQS, and the data DQ can be reversed in sequence.
Furthermore, workings of the PLL, and the DLL will vary depending on environmental conditions of the device, such as circuit noises, variation in power supply, device temperature, and so forth, thereby causing a change in frequency and propagation delay. As a result, in the case of burst-read of a long data (row) exceeding 1 kbit, it will become impossible to maintain a given relationship with the clock being fed from the tester.